Certain problems are often encountered during the transmission of digital data. These problems include:    [1] When digital messages contain long strings of 0's or of 1's, these strings might be misinterpreted by the receiver, or cause other problems, and are therefore undesirable or forbidden. An example of such a forbidden bit sequence is a long string of 0's, which might be interpreted by the receiver as a communication line interruption or as a power off signal rather than as an actual sequence of 0's to be transmitted.    [2] It is desirable, due to electrical considerations, to transmit messages comprising of roughly equal numbers of 0 and 1 bits. However, the actual data to be transmitted may include long strings of 0's or of 1's, or it may include very different numbers of 0 and 1 bits.    [3] In addition, it may be desirable to make the transmitted data unintelligible, i.e. scrambled or encrypted, to a third party intercepting it.
To address these issues, it is known to change some of the 0 bits to 1 bits of the messages, and vice versa, before their transmission, by a process called scrambling.
Because scrambling of transmitted message changes the bytes and the overall message, it has to be reversed at the receiving station, thereby restoring the original bit sequence and the original message, i.e. descrambling. Many scrambling and descrambling (hereinafter “SD”) methods have been proposed and some are in use. Many SD methods, including the method required by the HDLC/ATM standard, are based on modulo-2 summing of each data bit in a data sequence to be scrambled and of a scrambling bit of a scrambling sequence, the modulo-2 summing result being the scrambled bit. A single modulo-2 summing operation could also be performed by a two-input XOR gate. Hereinafter, modulo-2 summing operation will be referred to as a “XOR” operation. XOR-ing of the scrambled data bit with the same scrambling bit restores the original data bit, i.e. descrambles it.
The SD system employed by the HDLC/ATM standard performs a XOR operation on the k-th message bit with the already scrambled (k−43)rd bit of the message, where “k” designates the ordinal number of a bit in any sequence of bits. The index “n” designates hereinbelow the ordinal number of a group of bits processed in parallel. The index “i” designates hereinbelow the ordinal number of a bit within a group of bits processed in parallel. “D(k)” designates hereinbelow the k-th input bit to be scrambled, or the k-th descrambled output bit, and “S(k)” designates hereinbelow the k-th scrambled bit. An initial random forty three bit sequence is used to permit the XOR-ing of the first message bits. This necessitates the storage by both the transmitter's scrambler and by the receiver's descrambler of at least the last forty three scrambled and transmitted bits in order to scramble and descramble the current and the subsequent communicated bits. The initial bit sequence used for the scrambling and the descrambling of the first forty three message bits is usually all zeroes and must be stored in both the scrambler and the descrambler.
The output of two successive XOR operations on a data bit by two identical scrambling bits is the initial data bit. Thus the first XOR operation operates on a first data bit input and on a scrambling bit, and generates a first output bit. The two inputs to the second XOR operation are the first output bit from the first XOR operation and the same scrambling bit and the output of the second XOR operation is the initial data bit. Therefore, a repeated application of the first XOR operations generates a scrambled bit sequence while a repeated application of a second XOR operations as described hereinabove restores or descrambles the original digital string.
According to the standard HDLC/ATM scrambling method, the scrambling of each bit in a sequence comprising the transmitted message is the output of a XOR gate whose two input bits are the k-th data bit of the string and the k-43rd scrambled bit of the sequence. This way each bit of the scrambled sequence to be transmitted is generated. The descrambling is done by operating on pairs of the scrambled string bits spaced apart by the same spacing of forty three. Other methods exist in which the data stream is operated on by a previously defined sequence of bits, usually called a polynomial.
The rate at which data can be serially transmitted over a single line connecting a transmitter and a receiver (serial rate) is often much higher than the data processing rate since the data processing includes many operations, such as storing, scrambling and descrambling of the data by the transmitter and the receiver. Thus the data processing rate is often a rate limiting step in such communications.
U.S. Pat. No. 5,163,092 and its continuation, U.S. Pat. No. 5,185,799 to John McNesby et al., describe a parallel scrambling method useful for a different standard, SONET. The aforementioned patents disclose a device in which a sequence of eight serially-transmitted data bits (one byte) is loaded into eight registers and then these bits are processed simultaneously according to the scrambling and descrambling algorithm of the standard disclosed therein. However, the disclosed methods are not useful for scrambling/descrambling of HDLC/ATM transmissions.